1. Field of the Invention
The present invention relates to a decoder circuit of a semiconductor memory device, and, more particularly, to the structures of address lines and predecode lines which can shorten the cycle time.
2. Description of the Related Art
The capacities of semiconductor memory devices like dynamic random access memories and static memories are becoming ever greater. To match the increment, the number of addresses for designating a memory address is increasing too. A conventional decoder circuit is separated into predecoders and main decoders in accordance with the increased number of addresses to reduce the burden on an address buffer or the like. The predecoders are further separated into a plurality of predecoder groups to which divided addresses are respectively input. Predecoded signals are then input to the main decoders.
The number of addresses is determined by the memory capacity and the structure of the output circuit. In dividing an address to a plurality of sub addresses, it is inevitable that the number of divided addresses does not become uniform. As a result, the capacitive loads of the address lines or the outputs of address buffers and the predecode lines or the outputs of predecoders vary from one divided group to another.
In general, a decoder circuit outputs its decoded output in response to an address latch signal or the like after an address signal to be input is settled. The time for one cycle therefore comprises a standby time (address transition time) from the input of the address signal to the settlement of the input of the decoder circuit and an address latching time for the output of the decoder circuit to become valid after settlement.
When predecoders are unevenly divided as mentioned above, the timing for settling the predecode lines or the inputs of the main decoders vary. This variation leads first to variations in the start times for the rising and falling of the predecode lines, secondly to a variation in the rising duration or the falling duration, and further to variations in the end times for the rising and falling of the predecode lines. Such variations demand a longer standby time (address transition time) for the input signals to the main decoders to be settled. This results in a longer cycle time, or a shorter address latching period if the cycle time is constant.